This phase is the floorplanning step where Pblocks are created and assigned to each logical hierarchy. This defines which resource the placer can use to implement the hierarchy of the design.
When creating a Pblock, verify that adequate resources are available, based on the synthesis of each hierarchy. This is verified by looking at the physical resources estimates table in the Pblock properties window. To view this table, select the Statistics tab, as shown in the following figure.
If there are any entries in red (which indicates that there are no resources
for a desired site type), the design cannot route. If the
%Utilization is high, the design might not
route. Floorplanning a design is the most time-consuming part of the isolation design
flow. This lab helps you to familiarize with the floorplanning from the GUI. It is very
important to understand the floorplanning rules and complexities that are associated
with floorplanning any design. You can refer to the following documents for design
guidance,
Vivado
Design Suite User Guide: Dynamic Function eXchange (UG909) and
Vivado
Design Suite User Guide: Hierarchical Design (UG905). You can find more details on
the IDF rules in
Isolation Design Flow for UltraScale+ FPGAs and Zynq
UltraScale+ MPSoCs (XAPP1335). Execute
the following steps. Alternatively, you can run phase5 Tcl script from Tcl Console by
typing source ./lab_phase5.tcl.
Floorplanning must be done in a non-routing view. Enter non-routing view by de-selecting the routing view icon from the device tab menu, as shown in the following figure.
- Right-click TOP_PS_WRAPPER from the Netlist window, click Floorplanning.
- Click Draw Pblock as shown in
the following figure. You get the option to select sites for the Pblock when you
move your mouse pointer to the device window.
- Move your mouse pointer to the top left corner of the PS and hold the mouse
left key and select PS PU and VCU PU. Release the mouse. Refer to
Isolation Design Flow for UltraScale+ FPGAs and Zynq
UltraScale+ MPSoCs (XAPP1335) for more knowledge on
Programmable Units (PUs). Next, the New Pblock
window opens. You can assign a name to the Pblock; for this lab, the
default name is being used. Ensure Assign selected
cells check box is checked, as shown in the following figure. Click
OK.
- Open the Physical Constraints window
from the Window menu, as shown in the
following figure. Now open the Pblock
Properties window by selecting the Pblock you created from the
Physical Constraints window. Select
the Statistics tab from the Pblock Properties window. The Physical Resource Estimates appears, as shown in
Figure
36. From the Physical Resource
Estimates, you get %Util.
Based on this, more resources to the Pblock are included. Note: AMD recommends including more resources to the Pblock than is required by design. Higher utilization (%Util) can lead to routing difficulty or an inability to route the design. The following are guidelines to help ensure the design successfully routes.
Slice < 50% BRAM/DSP < 75% Other bigger tiles like GT, PS8, IOs, PCIE < 100% - Go to the Properties tab in Pblock Properties window and ensure SNAPPING_MODE of the Pblock is FINE_GRAINED. Refer to the Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for more details on SNAPPING_MODE.
- Right-click the Pblock you just created and click Add Pblock Rectangle. More resources will be available for selection from the device window. Move the mouse pointer to the bottom right corner of the X0Y0 Clock-Region and hold the mouse left key to select till the top left corner of the X0Y0 Clock-Region and release the mouse. Next, Add Rectangle window opens.
- Click Select All.
- Click OK.
- Add IOBs to the Pblock by repeating step 5 and selecting HPIO PUs, as shown
in the following figure.
- Now look at the Physical Resource
Estimates section from the Pblock
Properties > Statistics tab. BRAMs and ICAP need to be added to
the Pblock, as shown in the following figure. Repeat Step 4 to add Config Center to the Pblock for ICAP, as seen in
Figure 40.
- The dis-continues Pblock will appear
after the preceding step. As there is a gap between Pblock rectangles, there are no
routes from one rectangle to the other rectangle without having a touch-down (PIP) in non-Pblock interconnects. Hence
routing tends to fail with the current floorplan. Refer to
Isolation Design Flow for UltraScale+ FPGAs and Zynq
UltraScale+ MPSoCs (XAPP1335) for more details on IDF
rules for routing. Pblock must be made continuous. Include the resources between the
two triangles by following Step 5. After completion, it looks like the following
figure.
- Include DSP PUs which are adjacent to
HPIO PUs in clock-regions X1Y0 and X1Y1 by repeating Step 5. Include resources in clock region XOY3
which falls between HDIO PU and HPIO PU. The completed Pblock looks like the
following figure.
- Create Pblock for MB1_WRAPPER by leaving valid fence with
Pblock_TOP_PS_WRAPPER. Refer to Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for more details on fence rules. Repeat step 1 and step 2 for MB1_WRAPPER by starting at the top side of the clock region X1Y3 after the HPIO PU leaves one PU for fence. Leave DSP-CLE PU column beside HPIO PU for fence and continue to select remaining sites in clock region X1Y3. Leave one PU fence at the bottom. There are two different types of PUs as fence, as shown in the following figure. - Ensure to check SNAPPING_MODE of Pblock is FINE_GRAINED from the Properties tab in the Pblock Properties window.
- Add more resources to the Pblock. Follow step 5 to perform this step. Add GT
PUs in clock regions X2Y2 and X2Y3. Add the remaining resources in X2Y2 and X2Y3.
Ensure to leave one PU fence with
pblock_TOP_PS_WRAPPER. The following figure shows how the Pblock looks like after the completion of this step. - Draw Pblocks for MB2_WRAPPER, MB3_WRAPPER, and MAILBOX_WRAPPER.MB1_WRAPPER
has routes with both MB2_WRAPPER and MB3_WRAPPER. So Pblocks of MB2_WRAPPER and
MB3_WRAPPER must be adjacent to pblock_MB1_WRAPPER otherwise routing can fail. With
the current floorplan, it is tough to create two Pblocks adjacent to
pblock_MB1_WRAPPER with valid fence between each Pblock. To solve this issue, we
need to add more resources to pblock_MB1_WRAPPER. By following step 5, you can add
the following ranges in the clock region X2Y1 to
pblock_MB1_WRAPPER, as shown in the following figure. Alternatively, you can use the resize_pblock command to add these ranges (using the command on the next page).
To add resources using resize_Pblock, run the following command from Tcl Console. You can refer to Figure 9.{SLICE_X50Y91:SLICE_X51Y118 SLICE_X52Y91:SLICE_X59Y119 RAMB18_X2Y38:RAMB18_X2Y47 DSP48E2_X12Y38:DSP48E2_X12Y47}resize_pblock pblock_MB1_WRAPPER -add {SLICE_X50Y91:SLICE_X51Y118 SLICE_X52Y91:SLICE_X59Y119 RAMB18_X2Y38:RAMB18_X2Y47 DSP48E2_X12Y38:DSP48E2_X12Y47} - Create pblock_MB2_WRAPPER for MB2_WRAPPER by following step 10 and including
the following ranges.
{ SLICE_X27Y61:SLICE_X47Y118 BUFCE_LEAF_X152Y4:BUFCE_LEAF_X271Y7 BUFCE_ROW_FSR_X29Y1:BUFCE_ROW_FSR_X59Y1 DSP48E2_X7Y26:DSP48E2_X11Y45 HARD_SYNC_X0Y2:HARD_SYNC_X3Y3 RAMB18_X0Y26:RAMB18_X1Y45 RAMB36_X0Y13:RAMB36_X1Y22 URAM288_X0Y20:URAM288_X0Y27}Alternatively, you can do the same from the Tcl Console by running the following commands.
create_pblock pblock_MB2_WRAPPER add_cells_to_pblock pblock_MB2_WRAPPER [get_cells [list design_1_i/MB2_WRAPPER]] resize_pblock pblock_MB2_WRAPPER -add {SLICE_X27Y61:SLICE_X47Y118 BUFCE_LEAF_X152Y4:BUFCE_LEAF_X271Y7 BUFCE_ROW_FSR_X29Y1:BUFCE_ROW_FSR_X59Y1 DSP48E2_X7Y26:DSP48E2_X11Y45 HARD_SYNC_X0Y2:HARD_SYNC_X3Y3 RAMB18_X0Y26:RAMB18_X1Y45 RAMB36_X0Y13:RAMB36_X1Y22 URAM288_X0Y20:URAM288_X0Y27}Note: Ensure SNAPPING_MODE of Pblock is FINE_GRAINED from the Properties tab of the Pblock Properties window. - Create pblock_MB3_WRAPPER for MB3_WRAPPER by following step 10 and including
following ranges. Ensure SNAPPING_MODE of
Pblock is FINE_GRAINED from the Properties tab of the Pblock Properties
window.
{ SLICE_X27Y0:SLICE_X59Y59 BUFCE_LEAF_X152Y0:BUFCE_LEAF_X335Y3 BUFCE_ROW_FSR_X29Y0:BUFCE_ROW_FSR_X71Y0 DSP48E2_X7Y0:DSP48E2_X12Y23 HARD_SYNC_X0Y0:HARD_SYNC_X5Y1 PCIE40E4_X0Y0:PCIE40E4_X0Y0 RAMB18_X0Y0:RAMB18_X2Y23 RAMB36_X0Y0:RAMB36_X2Y11 URAM288_X0Y0:URAM288_X0Y15 SLICE_X50Y60:SLICE_X59Y89 DSP48E2_X12Y24:DSP48E2_X12Y35 RAMB18_X2Y24:RAMB18_X2Y35 RAMB36_X2Y12:RAMB36_X2Y17 SLICE_X60Y0:SLICE_X60Y59 BUFCE_LEAF_X336Y0:BUFCE_LEAF_X343Y3 BUFCE_ROW_FSR_X72Y0:BUFCE_ROW_FSR_X72Y0 BUFG_GT_X0Y0:BUFG_GT_X0Y23 BUFG_GT_SYNC_X0Y0:BUFG_GT_SYNC_X0Y14 GTHE4_CHANNEL_X0Y0:GTHE4_CHANNEL_X0Y3 GTHE4_COMMON_X0Y0:GTHE4_COMMON_X0Y0}Alternatively, you can do the same from the Tcl Console by running the following commands.
create_pblock pblock_MB3_WRAPPER add_cells_to_pblock pblock_MB3_WRAPPER [get_cells [list design_1_i/MB3_WRAPPER]] resize_pblock pblock_MB3_WRAPPER -add {SLICE_X27Y0:SLICE_X59Y59 BUFCE_LEAF_X152Y0:BUFCE_LEAF_X335Y3 BUFCE_ROW_FSR_X29Y0:BUFCE_ROW_FSR_X71Y0 DSP48E2_X7Y0:DSP48E2_X12Y23 HARD_SYNC_X0Y0:HARD_SYNC_X5Y1 PCIE40E4_X0Y0:PCIE40E4_X0Y0 RAMB18_X0Y0:RAMB18_X2Y23 RAMB36_X0Y0:RAMB36_X2Y11 URAM288_X0Y0:URAM288_X0Y15} -locs keep_all resize_pblock pblock_MB3_WRAPPER -add {SLICE_X50Y60:SLICE_X59Y89 DSP48E2_X12Y24:DSP48E2_X12Y35 RAMB18_X2Y24:RAMB18_X2Y35 RAMB36_X2Y12:RAMB36_X2Y17} -locs keep_all resize_pblock pblock_MB3_WRAPPER -add {SLICE_X60Y0:SLICE_X60Y59 BUFCE_LEAF_X336Y0:BUFCE_LEAF_X343Y3 BUFCE_ROW_FSR_X72Y0:BUFCE_ROW_FSR_X72Y0 BUFG_GT_X0Y0:BUFG_GT_X0Y23 BUFG_GT_SYNC_X0Y0:BUFG_GT_SYNC_X0Y14 GTHE4_CHANNEL_X0Y0:GTHE4_CHANNEL_X0Y3 GTHE4_COMMON_X0Y0:GTHE4_COMMON_X0Y0} -locs keep_all set_property SNAPPING_MODE FINE_GRAINED [get_pblocks pblock_MB3_WRAPPER] - Create pblock_MAILBOX_WRAPPER for MAILBOX_WRAPPER by running the following
commands from Tcl Console.
create_pblock pblock_MAILBOX_WRAPPER add_cells_to_pblock pblock_MAILBOX_WRAPPER [get_cells [list design_1_i/MAILBOX_WRAPPER]] -clear_locs resize_pblock pblock_MAILBOX_WRAPPER -add {SLICE_X2Y181:SLICE_X9Y239 BUFCE_LEAF_X16Y12:BUFCE_LEAF_X55Y15 BUFCE_ROW_FSR_X3Y3:BUFCE_ROW_FSR_X11Y3 DSP48E2_X1Y74:DSP48E2_X2Y95} set_property SNAPPING_MODE FINE_GRAINED [get_pblocks pblock_MAILBOX_WRAPPER] - Your floorplanning is completed here. Run the following command in the Tcl
Console to highlight Pblocks, as shown in the following
figure.
set pblocks [get_pblocks *];set ci 1;foreach pblock $pblocks {highlight_objects -color_index [expr {1 + ($ci % 19)}] [get_pblocks $pblock]; incr ci} - Assign Package Pins. Open I/O Ports tab from Windows menu, as shown in the following figure. Ensure Fixed check box is enabled. Refer to
Isolation Design Flow for UltraScale+ FPGAs and Zynq
UltraScale+ MPSoCs (XAPP1335) for more details on IDF
rules for package pins assignment.
Table 1. Package Pin Assignments Ports I/O Std Package Pin reset_rtl_0 LVCMOS18 D12 diff_clock_rtl_0_clk_p DIFF_HSTL_I_DCI_18 L3 uart_rtl_0_rxd LVCMOS18 C12 uart_rtl_0_txd LVCMOS18 A12 - Save the design.