Phase 4 - Phase 4 - XAPP1336

Isolation Design Example for the Zynq UltraScale+ MPSoC (XAPP1336)

Document_ID
XAPP1336
Release_Date
2023-10-20
Revision
2.1 English

This phase synthesizes the design which supports and creates the actual logical resources needed to complete the design as shown in the following figures.

Figure 1. Phase 4 - Synthesize

Follow the steps listed here for synthesis. Alternatively, you can run phase4 Tcl script from the Tcl Console by typing source ./lab_phase4.tcl.

Launch Synthesis

  1. Under the Synthesis menu on the left of the Vivado GUI, select Run Synthesis. If prompted, save the design.
  2. When it is complete, change the check box to Open Synthesized Design and click OK.
  3. If asked to close the elaborated design before opening the synthesized design, you can do so by selecting Yes. This is a good practice because memory might be limited.
Figure 2. Synthesized Design