Phase 3 - Phase 3 - XAPP1336

Isolation Design Example for the Zynq UltraScale+ MPSoC (XAPP1336)
Document_ID
XAPP1336
Release_Date
2023-10-20
Revision
2.1 English

This phase performs the register transfer level (RTL) elaboration and then sets the HD.ISOLATED property for each hierarchical wrapper, as shown in the following figures. Setting HD.ISOLATED is the key property that changes the rule set for the Placer and Router driving an isolated design.

Follow the steps listed here for RTL elaboration, and also to set HD.ISOLATED property. Alternatively, you can run phase3 Tcl script from the Tcl Console by typing source ./lab_phase3.tcl.

The Simulation and the RTL Analysis sections are located underneath the IP integrator section.

  1. Click Open Elaborated Design. This launches the process. When this is complete, you can see a large block diagram labeled design_1_i. This is the default name generated by the IP integrator when you add the HDL wrapper.
  2. You can navigate your design by using the mouse pointer to expand the hierarchy using the + button on the top left of any of the block, as seen in the following figure (with one level expanded).
  3. Next, you need to add some attributes to tell the tools which modules are going to be isolated using the IDF. This is done with the HD.ISOLATED attribute. This attribute not only evokes the IDF routing rules, but also protects redundant modules from undesired optimization. Synthesis optimization cannot happen across an HD.ISOLATED boundary. It can happen within one, but that is typically desired.
  4. Expand the design_1_i instance in the Netlist tab so that you can see each of the modules you created in the IP integrator, as shown in the following figure.
  5. Select MAILBOX_WRAPPER.
    1. Right-click and select Cell Properties (if this window is not already visible).
    2. Select the Properties tab in the cell properties window.
    3. Click the + symbol and add the attribute HD.ISOLATED from the Add Properties pop-up window.
    4. Expand the newly added attribute and check the unchecked box, as shown in the following figure.
  6. Repeat the previous step for the MB1_WRAPPER, MB2_WRAPPER, MB3_WRAPPER, and TOP_PS_WRAPPER.
  7. Save the design and enter Top when requested to enter the file name of the AMD design constraints (XDC) file. Lastly, select OK.