Phase 2 - Phase 2 - XAPP1336

Isolation Design Example for the Zynq UltraScale+ MPSoC (XAPP1336)
Document_ID
XAPP1336
Release_Date
2023-10-20
Revision
2.1 English

This phase adds wrappers to each of the three MicroBlaze™ containers, creating three hierarchies, and also creates two more hierarchies—one for the mailbox and the other for the PS, as shown in Figure 24. This allows the tools to split nets between isolated blocks which is required for a multi-region net. Such a net needs to be split so that a fault from a block affecting that net cannot fault any other block. You may refer to Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for more information on net-splitting.

The following steps specify how to add the wrappers. Alternatively, you can run phase2 Tcl script from Tcl Console by typing source ./lab_phase2.tcl.

Important: IPI introduces some design complexities by automatically adding DONT_TOUCH properties on every design block of an IPI design. This conflicts with IDF where multi-regional nets are concerned. To split multi-regional nets to meet IDF rules, the tools must modify the design by adding LUT buffers. However, DONT_TOUCH prevents any modification by the tools. Much of this complexity can be minimized by adding a wrapper around modules intended for isolation. Ultimately, it is the wrapper that is marked as isolated. Such wrappers are not required for custom HDL designs not implemented using IPI.
  1. In the Diagram canvas, right-click MB1 and select Create Hierarchy….
    1. Name it MB1_WRAPPER.
    2. Ensure the check box Move MB1 selected block to new hierarchy is selected, and then select OK.
  2. Repeat the previous step for MB2 naming MB2_WRAPPER.
  3. Repeat Step 1 for MB3 naming MB3_WRAPPER.
  4. Repeat Step 1 for mailbox_0 naming MAILBOX_WRAPPER.
  5. Repeat Step 1 for zynq_ultra_ps_e_0, tmr_sem_0, axi_uartlite_0, tmr_voter_AXI4LITE_0, tmr_voter_AXI4LITE_2, axi_interconnect_0 and axi_interconnect_1 by simultaneously selecting all of them and naming it TOP_PS_WRAPPER. After completing the preceding steps as mentioned, the design splits into five hierarchies, as shown in the following figure.
  6. Verify all connections are valid by right-clicking the blank canvas. Select Validate Design and click OK to continue.
  7. Save the design.
  8. Generate all necessary output products for the block design you just created.
    1. In the Sources tab, right-click design_1, and select Create HDL Wrapper, as shown in Figure 25. On the pop-up window, select Let Vivado manage the wrapper and auto-update and select OK.
    2. Under the IP integrator menu on the left, select Generate Block Design as shown in the following figure. Select Generate on the pop-up window. Select OK when the process completes. Keep the default values for Systhesis Options.

      The design is now ready for the RTL elaboration phase.

  9. Save the design.