Phase 1 - Phase 1 - XAPP1336

Isolation Design Example for the Zynq UltraScale+ MPSoC (XAPP1336)
Document_ID
XAPP1336
Release_Date
2023-10-20
Revision
2.1 English

To create the project, use IP integrator in the first phase. A single-instance of a MicroBlaze™ processor system and the processing system (PS) are instantiated. The hierarchy is created for the MicroBlaze processor, followed by the instantiation of the TMR Manager, which is used to create the triple mode redundancy (TMR), as shown in the following figure.

Figure 1. Phase1 - Create Design and Generate Block Diagram
  1. Create a target design folder. For this example, use ZUP_LAB.
  2. Copy the eight lab scripts (lab_phase1.tcl through lab_phase8.tcl) into the target design folder.
  3. Start AMD Vivado™ Design Suite version 2018.3 or a newer version.
  4. In the Tcl Console, point the console input to the design folder.
  5. Perform the following steps to generate and build the project. Alternatively, you can run phase1 Tcl script from the Tcl Console, by typing source ./lab_phase1.tcl.