The Zynq UltraScale+ Isolation Design Flow (IDF) rules are outlined in the Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335).
This lab gives details on how functions are to be isolated, specific differences between a normal hierarchical design flow and an IDF hierarchical design flow, information on IDF-specific hardware description language (HDL) code mnemonics, and trusted routing rules.
To illustrate the IDF and its capabilities, this design implements an isolated, triple modular redundant MicroBlaze processing subsystem, which communicates to the Arm® Cortex®-R5F core in the Low Power Domain. Refer to the Triple Modular Redundancy (TMR) LogiCORE IP Product Guide (PG268) for TMR guidance. The following figure shows a hierarchical diagram of the sub-blocks used in the implementation of this design.