Creating an IPI Block Design - Creating an IPI Block Design - XAPP1336

Isolation Design Example for the Zynq UltraScale+ MPSoC (XAPP1336)
Document_ID
XAPP1336
Release_Date
2023-10-20
Revision
2.1 English
  1. Click Create Block Design under IP INTEGRATOR menu. Refer to the previous figure (Figure 8).
  2. Keep the default design name design_1 and select OK. Refer to the following figure.
  3. You should be able to see a blank diagram. Refer to the following figure.
  4. Right-click in the Diagram canvas and select Add IP. Alternatively, you can click the + symbol at the center of the blank diagram.
  5. Scroll to the MicroBlaze IP, select it, and press Enter. Refer to Figure 11 and Figure 12.
  6. Click Run Block Automation located on top of the diagram window. Refer to the following figure.
  7. Select the following values in the Run Block Automation window.
  8. Click OK. Refer to the following figure.
    • Preset- None
    • Local memory- 32KB
    • Local memory ECC- None
    • Cache configuration- None
    • Debug module- None
    • Peripheral AXI port- Enabled
    • Clock connection- New clocking wizard
  9. Once block automation finishes, Run Connection Automation option appears. Click Run Connection Automation. Refer to the following figure.
  10. Select clk_wiz_1 from drop-down and click OK. Refer to the following figure.
  11. Add AXI Uartlite IP by right-clicking in diagram canvas and then select, and click Add IP, and then select AXI Uartlite.
  12. Next, click Run Connection Automation, select axi_uartlite_0 and click OK.
  13. This will create an AXI Interconnect IP. Change the name of the IP to axi_interconnect_0 by selecting the Interconnect IP and then changing the name on Sub-block Properties window. Alternatively you can run the following command from Tcl console.
     set_property name axi_interconnect_0 [get_bd_cells microblaze_0_axi_periph]
  14. Add Mailbox IP by right-clicking in the Diagram canvas and clicking on Add IP. Then select click Mailbox.
  15. Click Run Connection Automation and then select S0_AXI of mailbox_0 and click OK. Refer to the following figure.
  16. Add Zynq UltraScale+ MPSOC and AXI Interconnect IP by right-clicking diagram canvas and click Add IP.
  17. Customize axi_interconnect_1 IP to Number of Master Interfaces to 1. To customize, double-click axi_interconnect_1 IP. It opens the re-customize IP window. Refer to the following figure. Select 1 for the Number of Master Interfaces from the drop-down menu and click OK.
  18. Make the following connections:
    • S00_AXI of axi_interconnect_1 to M_AXI_HPM0_LPD of zynq_ultra_ps_e_0.
    • M00_AXI of axi_interconnect_1 to S1_AXI of mailbox_0.
    • ext_reset_in of rst_clk_wiz_1_100M to pl_resetn0 of zynq_ultra_ps_e_0.
    • maxihpm0_lpd_aclk of zynq_ultra_ps_e_0 to clk_out1 of clk_wiz_1.
    • ACLK of axi_interconnect_1 to clk_out1 of clk_wiz_1.
    • S00_ACLK of axi_interconnect_1 to clk_out1 of clk_wiz_1.
    • M00_ACLK of axi_interconnect_1 to clk_out1 of clk_wiz_1.
    • ARESETN of axi_interconnect_1 to interconnect_aresetn of rst_clk_wiz_1_100M.
    • S00_ARESETN of axi_interconnect_1 to peripheral_aresetn of rst_clk_wiz_1_100M.
    • M00_ARESETN of axi_interconnect_1 to peripheral_aresetn of rst_clk_wiz_1_100M.
    • S1_AXI_ACLK of mailbox_0 to clk_out1 of clk_wiz_1.
    • S1_AXI_ARESETN of mailbox_0 to peripheral_aresetn of rst_clk_wiz_1_100M.
  19. Assign the address by running assign_bd_address command from Tcl Console. Refer to Figure 8 for the location of the Tcl Console.
  20. Right-click an empty space in the diagram canvas and select Regenerate Layout. When you are finished, the IPI canvas will be re-organized to resemble the following figure.