Vivado Isolation Verifier (VIV) Checks 1, 2, 3, and 4 - Vivado Isolation Verifier (VIV) Checks 1, 2, 3, and 4 - 2.3 English - XAPP1335

VIV verifies that an FPGA design partitioned into isolated Pblocks meets stringent standards for fail-safe design. VIV is a collection of six design rule checks (DRCs) intended to aid FPGA developers in producing and documenting fault-tolerant FPGA applications developed with the IDF. Historically, VIV (VIV1) was a Tcl script that ran in the Vivado tools framework in the form of user defined DRCs. As part of adding support of the IDF for UltraScale+ architecture, AMD has released VIV2, which has the same set of six DRCs, but they are now are a part of the Vivado Design Suite built-in system DRCs. For convenience, in this application note VIV2 is referred to as VIV.

VIV 2.0 is available from the Vivado Design Suite 2018.3. Before the Vivado Design Suite version 2021.1, you need to enable VIV by setting a parameter hd.enableIDFDRC to True. But from Vivado version 2021.1 onwards, VIV gets enabled automatically when the tool detects the HD.ISOLATED property is set to True. Refer to Vivado Isolation Verifier User Guide (UG1291) for more detailed information on VIV2.