Synthesis - Synthesis - 2.3 English - XAPP1335
Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)
Document_ID
XAPP1335
Release_Date
2026-08-04
Revision
2.3 English
This step creates the actual logic that is used to implement your design.