Summary - Summary - 2.3 English - XAPP1335

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document_ID
XAPP1335
Release_Date
2026-08-04
Revision
2.3 English

This application note describes how to implement security-critical or safety-critical designs using the AMD Isolation Design Flow (IDF) with the AMD Vivado™ Design Suite. Design applications include information assurance (single-chip cryptography), avionics, automotive, and industrial applications. This document explains how to address the following objectives:

  • Implement isolated functions in an AMD Zynq™ UltraScale+™ MPSoC or an AMD UltraScale+™ FPGA
  • Verify the isolation using the AMD Vivado Isolation Verifier (VIV)
Note: Refer to Vivado Isolation Verifier User Guide (UG1291) for a list of all supported devices and Vivado Design Suite versions

You can purchase the Security Monitor IP core Product Brief developed by AMD to add additional security to your design. For more information, contact your local AMD representative to access these documents.

An example design is provided in the Isolation Design Example for Zynq UltraScale+ MPSoC Application Note (XAPP1336). For more information, see Isolation Design Example.