Revision History - Revision History - 2.3 English - XAPP1335

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document_ID
XAPP1335
Release_Date
2026-08-04
Revision
2.3 English

The following table shows the revision history for this document.

Section Revision Summary
08/04/2026 Version 2.3
Summary Removed specific version requirement for the Vivado Design Suite.
Common Terminology Updated figures.
Programmable Unit Sizes Updated Table 1.
Programmable Unit Size Examples Added note following Figure 8.
HDIO versus HPIO PUs Added description of HDIO tiles and figures.
Overview of IDF+DFX Added note clarifying there is no IDF+DFX support for Spartan UltraScale+ devices
Fence for SSI Technology Devices, SSI Technology Fence with Communication Between Isolated Modules, Drawing Pblocks Using the Vivado Design Suite GUI Updated title.
Vivado Isolation Verifier (VIV) Checks 1, 2, 3, and 4 Made Step 2 into two steps.
Vivado Isolation Verifier (VIV) Checks 5 and 6 Made topic into a procedure.
Gaps in the Floorplan Added links to figures.
Floorplan Rules and Guidance Updated nested blocks description.
05/15/2023 Version 2.2
Throughout document Defined Vivado 2021.2 applications.
Hints and Guidelines Added new sub-sections for:
  • Guidelines for using isolated Local Clock Net
  • Netlist
  • Clock Root Selection
  • Pblock Horizontal Edges
IDF+DFX Added new sub-sections for Block Design Container
03/09/2021 Version 2.1
IDF+DFX Added several new sections and images for more clarity on combined IDF+DFX flow.
10/09/2020 Version 2.0
Isolation Properties, Isolation Modules, and Communication Between Isolated Modules Added new sections for more clarity on the HD.ISOLATED and HD.ISOLATED_EXEMPTION properties.
Derived Range and Snapping Mode Added new sections for more clarity on how placement and routing resources are added in Pblocks.
Mapping the Logical Ownership to the Physical Ownership Added a new section for more clarity on link between logical and physical view for IDF flow.
Off-Chip Communication – Input/Output Buffer Control Added a new section for more clarity.
Isolation Fence Fence Around Processor Subsystem for Zynq UltraScale+ Devices and Fence for SSI Technology Devices Renamed Fence to Isolation Fence and added new content to clarify few key concepts with reference to Fence.
Floorplanning: Drawing Pblocks Using Tcl Commands and Constraints Added a new section for more clarity.
Design Guidance, Hints and Guidelines, and IDF Rules Checklist Added new sections to provide better understanding of IDF and its rules.
Added new content to the existing sections and images for clarity and all-around enhancement to the IDF concepts in this application note.
04/15/2019 Version 1.1
Summary and Conclusion Added coverage for the Zynq UltraScale+ MPSoC
02/15/2019 Version 1.0
Initial release. N/A