A key difference between the UltraScale+ architecture and previous architectures supported by the IDF is the use of back-to-back (B2B) interconnect tiles. Where previously one logic tile (CLE, block RAM, DSP, etc.) was associated with one or more dedicated interconnect tiles (INT column), UltraScale+ interconnect tiles service two distinct logic tiles (one on the left and one on the right of the INT column). This group of tiles along with their shared interconnect is called a programmable unit (PU).
Thus, a PU is a set of logical tiles such as CLEs, BRAMs, and DSPs, along with their shared interconnect tiles. For example, one BRAM, five CLEs, and five interconnect tiles shared between the BRAM and CLEs constitute one PU. For the sake of convenience, this can be called the BRAM PU. Another instance of a PU can be a CLE and CLM tiles on either side of a shared Interconnect (INT) tile. Example of PUs are listed under Programmable Unit Sizes.
You can think of a Pblock as a region in the FPGA which is made up of PUs, while creating isolated designs. For the IDF, a PU is the smallest logic building block that can be assigned to a Pblock. A Pblock is created by adding multiples PUs (as required) into it.
You must include the whole PU inside the Pblock while reserving resources during floorplanning. From the IDF perspective, having a part of the PU outside of the Pblock (for example, having a CLE tile of BRAM PU not included inside the Pblock) renders the whole PU (in this case the whole block RAM PU - block RAM, the interconnects, and the CLE tiles) unusable for the Vivado tools during the implementation stage. This is deliberate in IDF design because all the tiles within a PU share INT tiles, and isolation tools cannot place logic in a tile unless the complete PU of that tile is in an isolated Pblock. To grab all the resources of a PU inside a Pblock, the snapping mode property of the Pblock must be set to FINE_GRAINED. See Derived Range and Snapping Mode for a detailed explanation.