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Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document_ID
XAPP1335
Release_Date
2026-08-04
Revision
2.3 English

The driver of the clock net and all the loads of the clock net must be primitive cells under IDF module hierarchy (that is, the parent module where the HD.ISOLATED property is set).

Figure 1. IDF Module