HDIO versus HPIO PUs - HDIO versus HPIO PUs - 2.3 English - XAPP1335

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)
Document_ID
XAPP1335
Release_Date
2026-08-04
Revision
2.3 English

HDIO

As listed in Table 1, HDIO has the following fence rule:

  • Minimum fence width (vertical fence) is ½ HDIO
  • Minimum fence height (horizontal fence) is ½ HDIO PU

HDIO PU is a special PU where half of it can be used as a fence. That also means half of it can be included in a Pblock. HDIO tiles that share with the CMT have the following fence rules

  • The minimum fence width (vertical fence) is one HDIO PU.
  • The minimum fence height (horizontal fence) is one HDIO PU

An HDIO tile, along with the CMT, the HDIO PU, and the HDIO tile components consist of CLEs sharing the interconnects with HDIO tile. This whole PU must be used as fence whenever isolation is needed. The following figure shows the HDIO PU with all the component tiles.

Figure 1. HDIO PU with All the Sub-Components

As with any other PUs, for IDF design, two HDIO PUs belonging to two different isolated Pblocks cannot be adjacent to each other. They need at least one unprogrammed HDIO PU (not included in any Pblock) as a fence between them. The following figure shows a valid fence between two HDIOs belonging to two different isolated Pblocks.

Figure 2. Green and Blue Isolated Pblocks Separated by an HDIO PU Fence

HPIO

As listed in Table 1, HPIO has the following fence rule:

  • Minimum fence width (vertical fence) is 1 HPIO PU
  • Minimum fence height (horizontal fence) is 1 HPIO PU

A HPIO tile consists of four XiPHYs and a CMT along with the IOBs. And the HPIO PU, in addition to the HPIO tile components consists of CLEs sharing the interconnects with HPIO tile. This whole PU must be used as fence whenever isolation is needed. The following figure shows the HPIO PU with all the component tiles.

Figure 3. HPIO PU with All the Sub-Components
Note: Individual tiles of HPIO such as XiPHY and CMT cannot be used as fence, whenever needed the entire HPIO PU must be used for fence.

As with any other PUs, for IDF design, two HPIO PUs belonging to two different isolated Pblocks cannot be adjacent to each other. They need at least one HPIO PU (not included in any Pblock) as a fence between them. The following figure shows a valid fence between two HPIOs belonging to two different isolated Pblocks.

Figure 4. Green and Blue Isolated Pblocks Separated by an HPIO PU Fence
Note: While it is understood that the user will incur a huge penalty while using HPIO PU as fence by not being able to use 52 IO pins, this is needed to achieve isolation as the CMT of HPIO spans the complete PU, and it shares interconnect with all the tiles in the HPIO PU.