There are apparent gaps in the floorplan as seen by the Vivado tools Device window's Routing Resources view (refer to Figure 1, Figure 1, and Figure 1). These gaps are an artifact of how the software model is depicted in the Vivado IDE. Such gaps do not represent any form of isolation and cannot be used as a fence because they are not, in fact a PU/tile at all.
The following are the most common gaps seen in the floorplan:
- RCLK row (regional clock row)
- Configuration blocks near the center of the device floorplan
- Boundary of clock regions