Design Process - Design Process - 2.3 English - XAPP1335

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document_ID
XAPP1335
Release_Date
2026-08-04
Revision
2.3 English

The IDF software methodology allows for logical and physical separation of hierarchical designs. As mentioned before, there are many applications requiring IDF, such as government-grade cryptographic systems, safety-critical applications, and high-availability systems. The following figure shows the recommended process for a design using the IDF. These steps are key to achieve single-fault hardware isolation required in Information Assurance and Functional Safety designs. The IDF is not that different from a traditional design flow. The following figure shows a flow diagram of both flows–standard and IDF side by side for the Vivado tools.

Figure 1. Design Flow Chart for IDF