Boundary of Clock Regions - Boundary of Clock Regions - 2.3 English - XAPP1335

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document_ID
XAPP1335
Release_Date
2026-08-04
Revision
2.3 English

Gaps can be seen at the boundary of the clock regions. These are not valid fences and do not provide any isolation. The following figure shows such a gap as that is seen in the Vivado Design Suite GUI.

Figure 1. Gap Between Two Clock Regions Highlighted in White Rectangle That Looks like a Fence, but It Is Not