Software running on the MicroBlaze™ soft processor core drives the AXI Quad SPI core to read and write to SPI flash memory through the STARTUPE3 primitive. The software presents a command menu to the host computer running Tera Term through the AXI UART 16550 core. The menu provides commands to allow erasing, programming, and verifying SPI flash memory content. Software System Details describes the flash command set and software flow.
AMD Vivado™ Design Suite IP Integrator (IPI) creates a block diagram with the cores. The IPI block design and the STARTUPE3 primitive are instantiated within the top-level wrapper design file (design_1_wrapper.vhd) shown in the following figure.
Figure 1. Post-Configuration Reference Design System Block Diagram
