While the output pins of the STARTUPE3 block do not appear in the top-level design_1_wrapper.vhd wrapper, it is still necessary to ensure that the total path delays for the signals going into or coming out of the STARTUPE3 block meet timing requirements.
The fixed delay of the STARTUPE3 primitive is not automatically considered by
timing tool analysis, and the user constraints must be written to take this into
account. Because the timing tools assume user design timing ends at the USRCCLKO port, it is not possible to create a generated
clock on the external CCLK pin. Instead, a generated clock is created on the USRCCLKO port that takes the STARTUPE3 delay, board
delay, and setup time requirements for the SPI flash into account. The following
figure shows the timing paths that needs to be considered.
To reduce the delay on the clock traveling from the design logic to the USRCCLKO pin, use the set_max_delay constraint. The data
and 3-state signal paths to and from the STARTUPE3 primitive are constrained using
set_output_delay and set_input_delay constraints with respect to the generated clock
on the USRCCLKO pin. To show how the constraints
are created, the delays of the STARTUPE3 block and the setup requirements of the SPI
flash memory are obtained from the
Kintex
UltraScale FPGAs Data Sheet: DC and AC Switching
Characteristics (DS892) and the Micron Serial NOR Flash Memory
MT25QU256ABA Data Sheet (
www.micron.com). Sample parameters are provided in the
following tables to be used for the constraints.
| Symbol | Description | VCCINT Operating Voltage = 0.95V | Units |
|---|---|---|---|
| -2 Speed Grade | |||
| STARTUPE3 Ports | |||
| TUSRCCLKO | STARTUPE3 USRCCLKO input port to CCLK pin output delay | 1.00/6.70 | ns, Min/Max |
| TDO | DO[3:0] ports to D03-D00 pins output delay | 1.00/7.70 | ns, Min/Max |
| TDTS | DTS[3:0] ports to D03-D00 pins 3-state delays | 1.00/8.30 | ns, Min/Max |
| TFCSBO | FCSBO port to FCS_B pin output delay | 1.00/8.00 | ns, Min/Max |
| TFCSBTS | FCSBTS port to FCS_B pin 3-state delay | 1.00/8.00 | ns, Min/Max |
| TDI | D03-D00 pins to DI[3:0] ports input delay | 0.5/3.1 | ns, Min/Max |
| Symbol | XDC Names | Descriptions | Units |
|---|---|---|---|
| TCLQX (min) | Tco_min | Output hold time (clock LOW) | 1 ns |
| TCLQV (max) | Tco_max | Clock LOW to output valid under 30pF (DTR) | 6 ns |
| TDVCH (min) | Tsu | Data in setup time | 1.75 ns |
| TCHDX (min) | Th | Data in hold time | 2 ns |
Example constraints for the KCU105 board are shown below. The timing delays for the board, and the Micron MT25QU256ABA flash memory are obtained from measurement and the flash data sheet. The Micron SPI flash memory MT25QU256ABA is compatible with the Micron SPI flash memory N25Q256A11.
##### STARTUPE3 parameters
set cclk_delay 6.7 # Tusrcclko maximum value
##### MT25QU256 SPI device parameters set tco_min 1 # MIN Tco
set tco_max 6 # MAX Tco
set tsu 1.75 # SPI setup time requirement set th 2 # SPI hold time requirement
#### BOARD parameters-assumes data trace lengths are matched set tdata_trace_delay_max 0.25
set tdata_trace_delay_min 0.25
set tclk_trace_delay_max 0.2
set tclk_trace_delay_min 0.2 #### Constraints
# Define a SCK Clock for the Quad SPI IP. Following command creates a divide by 2 clock. #It also takes into account the delay added by STARTUP block to route the CCLK
create_generated_clock -name clk_sck -source [get_pins -hierarchical
*axi_quad_spi_0/ext_spi_clk] -edges {3 5 7} -edge_shift [list $cclk_delay $cclk_delay
$cclk_delay] [get_pins -hierarchical *USRCCLKO]
set_multicycle_path -setup -from clk_sck -to [get_clocks -of_objects [get_pins
-hierarchical */ext_spi_clk]] 2
set_multicycle_path -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins
-hierarchical */ext_spi_clk]] 1
set_multicycle_path -setup -start -from [get_clocks -of_objects [get_pins -hierarchical
*/ext_spi_clk]] -to clk_sck 2
set_multicycle_path -hold -from [get_clocks -of_objects [get_pins -hierarchical
*/ext_spi_clk]] -to clk_sck 1
# Max delay constraints are used to instruct the tool to place IP near the STARTUPE3 #primitive. If needed adjust the delays appropriately. The data path is defined by the #clock source of ext_spi_clk and is connected from the DDR MMCM UI Clock output #design_1_ddr4_0_1_c0_ddr4_ui_clk
set_max_delay -from [get_pins -hier {*STARTUP*_inst/DI[*]}] 1.000 -datapath_only set_max_delay -from [get_clocks design_1_ddr4_0_1_c0_ddr4_ui_clk] -to [get_pins -hier
{*STARTUP*_inst/USRCCLKO}] 1.000 -datapath_only
set_max_delay -from [get_clocks design_1_ddr4_0_1_c0_ddr4_ui_clk] -to [get_pins -hier
{*STARTUP*_inst/DO[*] {*STARTUP*_inst/DTS[*]}] 1.000 -datapath_only
These constraints account for the path delay to and from the AXI Quad SPI logic, the setup and hold requirements of the SPI flash memory, the FPGA I/O port delays, the STARTUPE3 primitive delays, and the board trace delays. The timing constraints for the reference design are included in the kcu105.xdc constraints file.