STARTUPE3 Primitive - XAPP1280

The dedicated AMD UltraScale™ FPGA SPI interface signals (RDWR_FCS_B_0, CCLK_0, D03_0, D02_0, D01_DIN_0, D00_MOSI_0) reside in Bank0. By default, these pins are not accessible for post-configuration access of the SPI flash memory. To access these dedicated pins, the design instantiates the STARTUPE3 primitive. The following table shows the internal logic signal name associated with each dedicated configuration pin, the STARTUPE3 port it connects to, and the corresponding FPGA output pin location.

The STARTUPE3 primitive allows a user design to drive or 3-state the FPGA outputs on the dedicated pins by connecting the design to the appropriate STARTUPE3 ports. In addition, D[03:00] can be read as inputs. The dedicated FPGA pins are accessed by the user design through the .USRCCLKO, .USRCCLKTS, .DO, .DTS, .FCSBO, and .FCSBTS ports of the STARTUPE3 block. The data signals returning from the SPI flash are provided to the user design through the .DI port. The UltraScale FPGA pins CCLK, D00_MOSI_0, D01_DIN_0, D02_0, D03_0, and RDWR_FCS_B_0 are dedicated and not assigned in the constraints file because their physical locations cannot be altered.

For example, forwarding the spi_0_sck_o externally to the flash is accomplished by connecting it to the USRCCLKO port of the STARTUPE3 instantiation. There is no explicit port declaration for sck at the top level of the design because the CCLK output of the FPGA can only be accessed via connections to the STARTUPE3 block. The STARTUPE3 port USRCCLKTS controls the enable of the USRCCLKO, and is tied to 0 so that the CCLK signal is always actively driven out to the SPI flash memory. The signals going from the internal logic through the STARTUPE3 block to the dedicated external pins of the FPGA are not shown as top level ports of the design, and do not appear in the .xdc file.

Since the connections between the AXI Quad SPI core and the STARTUPE3 primitive are made inside the top-level design_1_wrapper.vhd wrapper, the STARTUPE3 block does not appear in the IP Integrator block design. The instantiation of the STARTUPE3 is shown below:

-- STARTUPE3: STARTUP Block
-- Kintex UltraScale+
-- Xilinx HDL Language Template, version 2022.2
STARTUPE3_inst : STARTUPE3
 -----------------------
 generic map
 (
 PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams.
 SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency (ns) for simulation
 )
 port map
 (
 USRCCLKO => spi_0_sck_o, -- 1-bit input: User CCLK input
 ----------
 CFGCLK => open, -- 1-bit output: Configuration internal oscillator clock output
 CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output
 EOS => startupe3_eos, -- 1-bit output: Active-High output signal indicating the End Of Startup
 PREQ => open, -- 1-bit output: PROGRAM request to fabric output
 ----------
 DO => flash_dq_o, -- 4-bit input: Allows control of the D pin output
 DI => flash_dq_i, -- 4-bit output: Allow receiving on the D input pin
 DTS => flash_dq_t, -- 4-bit input: Allows tristate of the D pin
 FCSBO => spi_0_ss_o_0(0),-- 1-bit input: Controls the FCS_B pin for flash access
 FCSBTS => spi_0_ss_t, -- 1-bit input: Tristate the FCS_B pin
 GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port)
 GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
 KEYCLEARB => '1', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
 PACK => '0', -- 1-bit input: PROGRAM acknowledge input
 USRCCLKTS => spi_0_sck_t, -- 1-bit input: User CCLK 3-state enable input
 USRDONEO => '1', -- 1-bit input: User DONE pin output control
 USRDONETS => '1' -- 1-bit input: User DONE 3-state enable output
 );
-- End of STARTUPE3_inst instantiation