SPI Configuration Mode Constraints - XAPP1280

UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3 (XAPP1280)

Document ID
XAPP1280
Release Date
2024-08-29
Revision
2.1.2 English

The correct properties must be used during golden.bin file generation to ensure a successful master SPI x4 configuration. The properties listed below are included in the reference .xdc constraint file supporting the KCU105 evaluation board 1.8V SPI flash. For additional details on the options see UltraScale Architecture Configuration User Guide (UG570) and SPI Configuration and Flash Programming in UltraScale FPGAs (XAPP1233).

set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] 
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] 
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] 
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design] 
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] 
set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] 
set_property BITSTREAM.CONFIG.TIMER_CFG 0x00050000 [current_design] 
set_property BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT Enable [current_design]
set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x00F50000 [current_design]