Revision History - XAPP1280

UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3 (XAPP1280)
Document ID
XAPP1280
Release Date
2024-08-29
Revision
2.1.2 English

The following table shows the revision history for this document.

Section Revision Summary
08/29/2024 Version 2.1.2
General updates Editorial updates only. No technical content updates.
08/27/2024 Version 2.1.1
General updates Editorial updates only. No technical content updates.
05/17/2023 Version 2.1
Hardware System Details Updated STARTUPE3 PACK port signal connection to GND in Figure 1.
05/10/2023 Version 2.0
N/A
  • Updated design version from AMD Vivado™ Design Suite and SDK IDE version 2016.1 to Vivado Design Suite and AMD Vitis™ IDE 2022.2.
  • Addressed path segmentation critical warning.
  • Updated design for MT25QU256 compatible with N25Q256A11E and updated DDR4 to MT40A256M16LY-062E.
06/02/2016 Version 1.1
N/A Updated document content and reference design files to support Vivado Design Suite 2016.1. Changed Vivado Design Suite version references from 2015.4 to 2016.1.
System Overview
  • Removed redundant AXI timer block in Figure 1.
  • Updated values in Table 1.
Hardware System Details Removed redundant AXI timer block in Figure 1 (same as AXI Interconnect block).
Generate Reference Design Project Updated the IMPORTANT note on page 8. Updated Figure 6. Updated tip on page 16.
Hardware System Details Updated STARTUPE3 parameters listing on page 28 and constraints on page 29.
Software System Details Updated Figure 2.
Checklist and Debug Tips Revised Checklist and Debug Tips number 5 and number 6.
04/15/2016 Version 1.0.1
N/A Corrected typographical errors and other minor edits.
04/05/2016 Version 1.0
Initial release. N/A