You can download the reference design files for this application note from the Xilinx website. The following table shows the reference design matrix.
| Parameter | Description |
|---|---|
| General | |
| Developer names | Advanced Micro Devices, Inc. |
| Target device | AMD Kintex™ UltraScale™ FPGA (XCKU040-2FFVA1156E) |
| Source code provided | Yes |
| Source code format | VHDL |
| Design uses code and IP cores from existing application notes and reference designs or third party | AMD Vivado™ Design Suite |
| Simulation | |
| Functional simulation performed | No |
| Timing simulation performed | No |
| Test bench used for functional and timing simulations | No |
| Test bench format | N/A |
| Simulator software/version used | N/A |
| SPICE/IBIS simulations | N/A |
| Implementation | |
| Synthesis software tools/versions used | Vivado synthesis |
| Implementation software tools/versions used | Vivado Design Suite and AMD Vitis™ IDE 2022.2 |
| Static timing analysis performed | Yes |
| Hardware Verification | |
| Hardware verified | Yes |
| Hardware platform used for verification | KCU105 evaluation board |