Introduction - XAPP1280

The reference design in this application note uses an AMD MicroBlaze™ soft processor core to interface to the AXI Quad SPI core and the STARTUPE3 primitive to implement post-configuration read and write access through a dedicated SPI interface to the on-board SPI flash memory. The following figure shows operation of the post-configuration reference design.

Figure 1. Reference Design Post-Configuration Access Flow

Important: This application note is not suitable for use with an update image that is a partial bitstream. Programming a partial bitstream uses a shutdown command that disables the USRCCLK0/USRCLKTS connection from the STARTUPE3 block and will disrupt SPI flash memory access.

When the SPI configuration mode is used to configure the FPGA, the initial bitstream image loads from the SPI flash memory. After the FPGA is initially configured, the SPI configuration interface typically remains unused. However, the unused space in the SPI flash memory can be used to store additional configuration images or application data, eliminating the cost of adding extra memory and using more board space. The preceding figure shows how the reference design executes this flow:

Step 1 configures the FPGA using the golden bitstream image (golden.bin) stored in the SPI flash memory. The golden bitstream image includes the STARTUPE3 primitive, interface logic, IP cores, and constraints to enable reading and writing to the unused storage in the SPI flash memory.
Step 2 runs application code on the MicroBlaze processor to download a new update bitstream from the computer by writing it into DDR4 memory temporarily and then moving it into the SPI flash memory. This step is controlled through the UART/Tera Term interface.
Step 3 reconfigures the FPGA using the update bitstream image (update.bin) stored in the SPI flash memory and replaces the original golden bitstream image (golden.bin).