IP Core Address Map - XAPP1280

UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3 (XAPP1280)
Document ID
XAPP1280
Release Date
2024-08-29
Revision
2.1.2 English
Table 1. IP Core Addresses
IP Core Version Input Clock Frequency Offset Address Range High Address
MicroBlaze Soft Processor (microblaze_0) 11.0 (Rev. 10) 100 MHz N/A N/A
DDR4 SDRAM MIG (ddr4_0) 2.2 (Rev. 17) 300 MHz 0x8000_0000 1 GB 0xBFFF_FFFF
AXI Quad SPI (axi_quad_spi_0) 3.2 (Rev. 26) 100 MHz 0x44A0_0000 64 KB 0x44A0_FFFF
AXI Block RAM Controller (axi_bram_ctrl_0) 4.1 (Rev. 7) 100 MHz 0xC000_0000 1 MB 0xC00F_FFFF
AXI Interrupt Controller (microblaze_0_axi_intc) 4.1 (Rev. 17) 100 MHz 0x4120_0000 64 KB 0x4120_FFFF
AXI UART 16550 (axi_uart16550_0) 2.0 (Rev. 29) 100 MHz 0x44A1_0000 64 KB 0x44A1_FFFF
AXI Interconnect (axi_mem_intercon) 2.1 (Rev. 28) 100 MHz N/A N/A
Processor System Reset Module (proc_sys_reset) 5.0 (Rev. 13) 100 MHz N/A N/A