Generate Reference Design Project - XAPP1280

UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3 (XAPP1280)
Document ID
XAPP1280
Release Date
2024-08-29
Revision
2.1.2 English
Follow these steps to generate a reference design project.
  1. Go to c:\xapp1280_quad_spi. Double-click run_kcu105.bat to run the batch file.

    This batch file generates the Vivado IPI hardware project (project_1.xpr) and exports the created hardware to Vitis (project_1.vitis) under the project_1 directory. The following figure shows the project directory addition.

    Tip: The project build takes approximately 90 minutes depending on host computer.


  2. Run the Vitis 2022.2 Integrated Design Environment (IDE) launcher from the AMD Design Tools. Ensure the workspace is selected as shown in the following figure and click Launch.

  3. Create an application for the Quad SPI flash memory read and write access:
    1. Select Create Application Project.
    2. In the Create a New Application Project window, click Next.
    3. Select the Create a new platform from hardware (XSA) tab and browse to select the design_1_wrapper.xsa as shown in the following figure.

    4. Click Next to open the applications project details window.
    5. Under Applications project name enter quad_spi_rw as shown in the following figure.

    6. Click Next to select the domain for your project.
    7. Click Next on the Domain window with settings as shown in the following figure.

    8. Select Empty Application (C) as shown in the following figure.

    9. Click Finish.
    10. Right-click src and select Import Sources as shown in the following figure.
      7 x 9 inches Sheet.1
    11. Browse to the C:\xapp1280_quad_spi\source directory, select folder. Then select the flash_qspi_rw.c and lscript.ld.

    12. Click Finish to add both files to the project and then click Yes when asked to Overwrite the lscript.ld in the quad_spi_rw\src folder.
    13. Under the Vitis Explorer navigation pane right-click quad_spi_fw and select Project > Build Project.
  4. (Optional Step) Review the MicroBlaze code: In the Vitis project explorer double-click flash_qspi_rw.c to open the file and review the MicroBlaze code. This code controls the UART/Tera Term command menu, defines the parameters of the SPI flash memory and controls reads and writes to memory:
    • The SPI flash memory commands and their definitions are located near the top of the code listing. The parameters and commands should match the targeted SPI flash memory device data sheet. The command sequences are described in Software System Details.
    • Flash-sizing information is located under “Number of bytes per page in the flash device.” This information includes definitions for the flash memory page size, number of sectors, bytes per sector and other information. These parameters should match the data sheet values for the targeted SPI flash memory device.
    • Descriptions of the functions that are used to build each menu operation are located under ”Function Prototypes“. The low level functions can be examined in detail by searching on the function name in the file. At the lowest level, all the operations that are needed for the flash memory can be created using six functions: SpiFlashWriteEnable(), SpiFlashWrite(), SpiFlashRead(), SpiFlashBulkErase(), SpiFlashGetStatus(), and SpiFlashQuadEnable().