Flash Command Set - XAPP1280

UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3 (XAPP1280)
Document ID
XAPP1280
Release Date
2024-08-29
Revision
2.1.2 English

There are a number of commands that provide access to the flash array or perform other operations on the SPI flash memory. All SPI transactions in master mode depend upon commands supported by a slave device connected to the AXI QUAD SPI core. Refer to the respective SPI flash memory data sheet for the supported commands. The Micron MT25QU256ABASPI flash memory commands are described in Micron Serial NOR Flash Memory N25Q256A11E and MT25Q256U Data Sheets (www.micron.com). This reference design provides user access to a subset of commands by way of the menu shown in Program SPI Flash Memory with update.bin. The commands implemented for the SPI flash on the KCU105 are shown in the flow diagrams in the following figures.

Figure 1. Flash Command Set Flow Diagram

The flowchart for Program/Verify (Program SPI Flash Memory with update.bin Tera Term main menu option 4).

Figure 2. Menu Option 4 (Program/Verify) Flow Diagram

Each of the supported operations shown in the Flow Diagrams has a specific command sequence. The command sequences are provided below for each of the major operations.

Write Enable Command Sequence

The write enable command must be issued before every write transaction (erase/program data to the flash/register write of flash) command to the flash. Disable the master transaction by asserting the master inhibit bit of SPI control register (SPICR) and reset the RX and TX FIFOs through SPICR. Example: Write 0x1E6 to SPICR.

  1. Issue the write enable command by writing 0x06 into SPI Data Transmit Register (SPIDTR).
  2. Issue chip select by writing 0x00 to SPI Slave Select Register (SPISSR).
  3. Enable master transaction by deasserting the SPICR, master inhibit bit.
  4. Deassert chip select by writing 0x01 to SPISSR.
  5. Disable master transaction by asserting the SPICR master inhibit bit.

Erase Command Sequence

  1. Reset RX and TX FIFOs through SPICR.
  2. Issue the bulk erase command to erase the entire flash followed by the flash base address. Example: Write 0xC7 to SPIDTR
  3. Issue chip select by writing 0x00 to SPISSR.
  4. Enable master transaction by deasserting the SPICR master inhibit bit.
  5. Deassert chip select by writing 0x01 to SPISSR.
  6. Disable master transaction by asserting the SPICR master inhibit bit.

Program Data Command Sequence

  1. Reset RX and TX FIFOs through SPICR.
  2. Issue the write data command into SPIDTR to write data into any specific sector followed by the flash sector address. Fill SPIDTR with the data to be written to flash. The maximum data size depends upon the configured QSPI FIFO size.
  3. Issue chip select by writing 0x00 to SPISSR. Enable master transaction by deasserting the SPICR master inhibit bit.
  4. Deassert chip select by writing 0x01 to SPISSR.
  5. Disable master transaction by asserting the SPICR master inhibit bit.

Read Data Command Sequence

  1. Reset RX and TX FIFOs through SPICR.
  2. Issue the read data command into SPIDTR to read data from any specific sector followed by the flash sector address. Fill SPIDTR with the dummy data to read required data from the flash.
  3. Issue chip select by writing 0x00 to SPISSR.
  4. Enable master transaction by deasserting the SPICR master inhibit bit.
  5. Deassert chip select by writing 0x01 to SPISSR.
  6. Disable master transaction by asserting SPICR master inhibit bit.
  7. Read SPIDRR, to get the read data that is received from the SPI bus.

The reference design menu option 4 performs Program > Verify with one selection (see the preceding figure). The verify is a read of the full .bin file compared to the original .bin contents. If an error is detected the address of the failure will be provided.

Program SPI Flash Memory with update.bin showcases option 4 in step 5, however, the Tera Term main menu also has individual operation options. When the individual operation option is selected (option 1, 2, 3, or 5) then the desired start address must be supplied along with either the stop address or number of bytes. An example read instruction is shown in the following figure.

Figure 3. Option 5: Read Quad SPI Flash Output