The AXI Quad SPI core is setup specifically for the AMD Kintex™ UltraScale™ XCKU040-2FFVA1156E FPGA, and the Micron MT25QU256ABA SPI flash memory on the KCU105 evaluation board. The IP Integrator window shown in the following figure is used for customization.
Figure 1. AXI Quad SPI Core Settings
The selections shown in the re-customization window are used by this application note reference design. The reason for the selections are described below:
- The Enable Performance Mode selects the AXI4 interface instead of the default AXI4-Lite interface. See AXI Quad SPI LogiCORE IP Product Guide (PG153) for more information.
- ID_WIDTH (Auto) 3 is used because the SPI flash memory in Quad mode only responds with three valid bytes for the multiple I/O read ID command.
- The Mode is set to the Quad to
support faster operation performance on the SPI flash with x4 data bus width instead
of the default serial x1 option.
Selecting quad mode also defaults:
- The data bus Transaction Width to 8 for standard instructions.
- The Frequency Ratio
is set to 2 to divide the 100 MHz clock on the
ext_spi_clkpin by 2. - Master Mode is selected because the AXI Quad SPI core is the SPI master.
- Enable FIFO is selected because the FIFO requires buffering in quad mode.
- No. of Slaves is set to 1 because the SPI flash memory is the only slave device.
- Micron (Numonyx) is selected in the Slave Device field because this is the type of SPI flash memory available on the KCU105 board.
- The Use STARTUP Primitive External to the IP is selected to make the connections to the STARTUPE3 primitive visible outside the AXI Quad SPI core.
Tip: Designs that require the use of the
STARTUPE3 primitive for multiple cores should use the STARTUPE3 external selection as
demonstrated in this reference design. The external option provides the most
flexibility. If a user design only requires STARTUPE3 port access with the AXI Quad SPI
core then the setting Use STARTUP primitive internal
to IP could be used.