Clock Topology - XAPP1280

UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3 (XAPP1280)
Document ID
XAPP1280
Release Date
2024-08-29
Revision
2.1.2 English

The reference design uses a 300 MHz differential clock input from a Silicon Labs Si5335A quad clock generator/buffer located on the KCU105 board. The clock distribution is shown in the following figure.

Figure 1. Reference Design Clocking Topology

The differential clock is supplied to a mixed-mode clock manager (MMCM) inside the DDR4 SDRAM interface that outputs 1,200 MHz, 300 MHz, and 100 MHz. The 1,200 MHz clock is supplied to the external DDR4 memory, the 300 MHz clock is supplied to the AXI Block RAM controller and AXI memory interconnect module, and the 100 MHz clock is supplied to the MicroBlaze™ interrupt controller, JTAG-to-AXI controller, local memory controller, AXI 16550 UART, AXI peripheral interconnect module, and the AXI Quad SPI Controller.

The AXI Quad SPI Controller core receives the 100 MHz clock and uses it to clock transactions on the AXI interface. Depending on the customization selections of the this module, the clock provided on the ext_spi_clk pin can be divided before being sent via the STARTUPE3 block to the clock input (C) of the SPI flash memory.

In the case of this reference design, the 100 MHz clock connected to the ext_spi_clk pin is divided by 2 to provide a 50 MHz clock to the SPI flash memory.

Important: This reference design is targeted for use with the Micron MT25QU256ABA SPI flash memory provided on the KCU105 evaluation board. If the design is modified for use with other SPI flash memories, the clock frequency supplied to the MicroBlaze system, and to the SPI flash memory via the STARTUPE3 block might require adjustment. The Micron SPI flash memory MT25QU256ABA is compatible with the Micron SPI flash memory N25Q256A11.