Checklist and Debug Tips - Checklist and Debug Tips - XAPP1280

UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3 (XAPP1280)
Document ID
XAPP1280
Release Date
2026-01-23
Revision
2.1.3 English
  1. When Customizing the AXI Quad SPI Core, verify Use STARTUP Primitive External to the IP selected for this demonstration (see Figure 1).
  2. Ensure Set Up KCU105 Board is completed before running the reference design demonstration. This will:
    • Ensure the board power is connected properly and power switch SW1 is in the ON position.
    • Master SPI configuration mode is properly set (Mode pins are set to M[2:0] = 001). See DIP switch SW15 settings shown in Figure 1.
    • Both UART and JTAG cables are connected from the KCU105 evaluation board to the host computer See Figure 1.
  3. If you do not see the Reference Design Main Menu displayed in Tera Term or if UART communication is not working between the host computer and the KCU105 board (J4), then verify the Tera Term and Computer COM port setup is correct:
    • Confirm proper COM port driver is selected in Windows Device Manager. Select the standard version, not the enhanced version (see the following figure). The COM number might be different on different computers. If the KCU105 System Controller Main Menu is displayed in Tera Term this is an indicator that the enhanced COM port was incorrectly selected instead of the standard COM port target.

    • Confirm Tera Term is installed correctly (version 4.105 was used for reference design testing).
    • Confirm COM port settings in the Tera Term Port Settings tab match the values shown in step 2 of Program SPI Flash Memory with update.bin.
  4. If the FPGA is not configuring:
    • Confirm a valid bitstream image is loaded into SPI memory
    • Start FPGA programming by momentarily pressing the FPGA PROG pushbutton SW4 or cycle power using SW1 (See Figure 1 for locations)
  5. If the batch files do not run correctly:
    • Ensure AMD Vivado™ Design Suite 2022.2 is installed and that the path is setup correctly.
  6. The DONE LED does not light and the Master SPI configuration mode is properly set on DIP switch SW15:
    1. Verify that the FPGA golden.bin can be programmed directly using the JTAG interface (J87).
    2. Perform a readback to check the contents of the SPI memory programmed at different locations.
    3. For user designs, ensure the write_bitstream constraints are implemented correctly for SPI mode as described in Hardware System Details.
    4. The DONE LED is lit, but the wrong pattern is loaded. Ensure that the right image was used when running the reference design. The pattern for the initial image (golden.bin) is LED0 blinking, and the pattern for the update image (update.bin) is LED1 blinking.
  7. This reference design uses operations that are targeted for the Micron MT25QU256ABA SPI flash memory. If your design is based on this reference design but targets a different flash memory, the design must be modified to support the different flash memory. Refer to the target flash vendor data sheet.
  8. If the Manufacturer ID (option 1) is not working, check the IDCODE via JTAG using the Xilinx Software Command-Line Tool (XSCT):
    1. Open XSCT command prompt by selecting Xilinx Design Tools > Xilinx Software Command Line Tool 2022.2.
    2. At the command line prompt XSCT% enter these commands:
      XSCT% enter these commands:

xsct% connect
xsct% fpga -f c:/xapp1280_quad_spi/ready_to_download/golden.bit xsct% ta 5
xsct% source xapp1280_quad_spi/source/xmd_idcode.tcl xsct% idcode

      The resulting output will look like this:

      Mfg ID:	44A0006C:	00000020
Memory	Type:44A0006C:	000000BB
Memory	Size:44A0006C:	00000019
Device	ID 1:44A0006C:	00000010
  9. An alternative to XSCT is to use the JTAG-to-AXI IP in the reference design. The JTAG-to-AXI IP enables the Vivado hardware manager to send low-level JTAG commands via the JTAG cable. To perform an IDCODE check on the SPI flash memory use the following Tcl command sequence.
    1. Start Vivado hardware manager.
    2. In the Tcl console type:
      connect_hw_server open_hw_target -jtag_mode 1
set current_hw_jtag [get_property hw_jtag [lindex [get_hw_targets] 0]] source jtag_to_qspi.tcl
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