AXI Quad SPI Core and STARTUPE3 Primitive - XAPP1280

UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3 (XAPP1280)

Document ID
XAPP1280
Release Date
2024-08-29
Revision
2.1.2 English

The connections required for post-configuration between the AXI Quad SPI core, the STARTUPE3 primitive, the FPGA SPI interface pins, and the external SPI flash are shown in the following figure.

Figure 1. AXI Quad SPI Core to STARTUPE3 Connectivity