Reference Design

Burst Clock Data Recovery for 1.25G/2.5G PON Applications in UltraScale Devices (XAPP1277)

Document ID
XAPP1277
Release Date
2024-01-05
Revision
1.2 English

Download the reference design files for this application note from the AMD website.

The following checklist indicates the procedures used for the provided reference design.

Table 1. Reference Design Matrix
Parameter Description
General
Developer name AMD
Target devices Kintex UltraScale and Virtex UltraScale FPGAs
Source code provided? Yes
Source code format (if provided) VHDL
Design uses code or IP from existing reference design, application note, third party or Vivado software? If yes, list. No
Simulation
Functional simulation performed Yes
Timing simulation performed? N/A
Test bench used for functional and timing simulation? Yes
Test bench format VHDL
Simulator software and version Mentor ModelSim 10.6
SPICE/IBIS simulations N/A
Implementation
Synthesis software tools/versions used Vivado Design Suite 2023.1
on software tool(s) and version Vivado Design Suite 2023.1
Static timing analysis performed? Yes
Hardware Verification
Hardware verified? Yes, cases 1 to 5
Platform used for verification KCU1250 characterization board