Hardware Test Bench on the KCU1250 Board

Burst Clock Data Recovery for 1.25G/2.5G PON Applications in UltraScale Devices (XAPP1277)

Document ID
XAPP1277
Release Date
2024-01-05
Revision
1.2 English

The hardware test bench is designed for the KCU1250 characterization board. (The KCU705 evaluation board can also be used for this purpose, but the AC coupling on the board prevents testing the BCDR at very low preamble lengths.)

Connect a Bulls Eye cable to Q226, and refclk_0 should be connected to a 155.52 MHz reference clock. This is the only clock that is used by the test bench. In Q226, the transmitter of channel 3 should be connected to the receiver of channel 3, in DC-coupled mode.

Run the script bcdr_design.tcl (in the directory tb_hw) from the AMD Vivado™ Design Suite, and generate the bitstream of the automatically created project. The FPGA can be programmed and the VIO GUI should be configured as shown in the following figure.

Figure 1. GUI of the BCDR Test Bench

The correct hardware operation is identified by the PAYLOAD_ERR being 0 and the packet number (FR_NM) constantly changing. This identifies the condition when packets are received and no errors are detected.

This test bench can stress the BCDR by setting EN_HAMMER to 1, which identifies the condition where packets have a 0.5 UI phase shift packet to packet. The preamble length can be programmed on the fly to verify the correct operation of the BCDR, even at very low preamble lengths. All debug signals from the BCDR can be monitored by an integrated logic analyzer (ILA) core, also present in the hardware test bench.