The BCDR circuit implementation described in this application note has these features:

- Fully synchronous design:
- 80- or 32-bit datapath
- Single clock architecture

Although the BCDR can operate over a wide range of clock frequencies, six typical cases are considered in this application note. The simulation test bench described in this application note is built according to the five cases listed in the following table.

Table 1. Five Possible Operating Modes of the BCDR Case No. Datapath Line Rate (Gb/s) Oversampling Rate SerDes REFCLK (MHz) 1 80 1.244 10 155.52 2 80 2.488 5 3 80 2.488 6 4 32 1.244 6 5 32 1.244 5 6 80 1.244 5 77.76 - Fully fractional design:
- The oversampling rate is programmable on-the-fly and can be a fraction or an integer.
- Fractional burst acquisition.
- Operates at both 1.244 Gb/s and 2.488 Gb/s burst operation rates.

The ratio between the oversampling rate and the data rate can be an integer or a fraction. This implies that the core can operate over a wide range of rates and reference clocks. The minimum recommended operating condition is to have an oversampling rate of 5.

- Programmable preamble and programmable length up to 32 bits:
- The preamble length identifies the minimum number of consecutive alternating bits to flag a preamble. When longer preambles are used by the network, multiple and consecutive preambles are flagged by the BCDR.

Tip: Keep the preamble length at 32. - Hitless programmable bandwidth during tracking:
- This core is able to track jitter during the payload, that is, outside of the burst area. To optimize robustness, the bandwidth is digitally user-adjustable, even at runtime.

- Programmable averaging level during burst acquisition of 1, 2, 4, or 8 clock
cycles:
- The statistical information in preambles longer than 32 bits can be used to increase the accuracy of phase estimation during the burst. Keep the number of bits lower than the preamble length specified by the OLT. The BCDR always uses the last part of the preamble to estimate the burst phase. For example, 8 clock cycles equals 128 bits for upstream in 2.5 Gb/s, 80-bit mode.

- Programmable preamble pattern:
- Up to two independent preamble patterns can be programmed, with lengths up to 32 bits.