Circuit Description and Usage Model

Burst Clock Data Recovery for 1.25G/2.5G PON Applications in UltraScale Devices (XAPP1277)

Document ID
XAPP1277
Release Date
2024-01-05
Revision
1.2 English

The following figure illustrates the BCDR architecture, showing the relevant inputs and outputs. The deserialized data (32- or 80-bit wide) flows in parallel into the lower branch (LB) and the upper branch (UB).

Figure 1. BCDR Simplified Architecture

The lower branch works on delayed data, continuously tuning the numerically controlled oscillator (NCO) to track the incoming data edges. Each raw sample is associated with a phase between –180 degrees and +180 degrees. The raw sample with the phase closest to 0 degrees (that is, closest to the middle of the eye diagram) is extracted by the sample selector block. The lower branch tracks phase variations with typical time constants that are much longer than the preamble time. Thus, the loop in the lower branch is expected to track phase changes or jitter, but not bursts.

The delay element allows the upper branch to recognize a preamble and estimate its phase by averaging the phase information of many consecutive edges. Upon recognizing the consecutive edges as a preamble, the NCO in the lower branch is steered in one single clock cycle to be aligned with the new packet. The lower branch never experiences a phase burst because the NCO is steered just before the burst enters the phase detector in the lower branch.

For debugging purposes, you can disable the burst injection capability by setting BURST_EN to 0. BCDR Simulation Test Bench further describes this item, which is the characterizing feature of a BCDR. The phase of the NCO can be monitored over time for debug purposes, both in simulation and in hardware, through the signal PHASE_OUT.

The following table describes the attributes of the BCDR core.

Table 1. BCDR Core Attributes
Attribute Type Description
DT_IN_WIDTH Integer Input datapath width. Can be 32 or 80.
DT_OUT_WIDTH Integer Output datapath width. Can be 8 or 32.
ENABLE_CENTER_F_ATTR Std_logic

When set to 1, CENTER_F_ATTR is used as CENTER_F.

When set to 0, the CENTER_F port is used.

CENTER_F_ATTR

Std_logic_vector

(36 downto 0)

The CENTER_F_ATTR is used when ENABLE_CENTERF_ATTR is set to 1.
EN_PAT_MSK_ATTR Std_logic

When set to 1, PAT_MSK_ATTR is used as PAT_MSK.

When set to 0, the PAT_MSK port is used.

PAT_MSK_ATTR

Std_logic_vector

(31 downto 0)

The PAT_MSK_ATTR attribute is used when EN_PAT_MSK_ATTR is set to 1.
EN_AVE_SEL_ATTR Std_logic

When set to 1, AVE_SEL_ATTR is used as AVE_SEL.

When set to 0, the AVE_SEL port is used.

AVE_SEL_ATTR

Std_logic_vector

(1 downto 0)

The AVE_SEL_ATTR is used when EN_AVE_SEL_ATTR is set to 1.
EN_BDW_ATTR Std_logic

When set to 1, BDW_ATTR is used as BDW.

When set to 0, the BDW port is used.

BDW_ATTR

Std_logic_vector

(3 downto 0)

The BDW_ATTR attribute is used when EN_BDW_ATTR is set to 1.
ENABLE_EN Std_logic When set to 1, the EN port is active for all internal processes.
EN_LTR_PORT Std_logic

When EN_LTR_PORT is set to 1, the LTR port is used to disable the lower branch.

When EN_LTR_PORT is set to 0, the lower branch is disabled.

ENABLE_DBG Std_logic When set to 1, debug output ports are enabled.
REDUCE_PD Std_logic When set to 1, allows resource reduction only in 10X mode.
USE_RED_BRICK Std_logic When set to 1, allows resource reduction only in 10X mode.
EN_PREAMBLE_ATTR Std_logic

When set to 1, PREAMBLE_ATTR_0 and PREAMBLE_ATTR_1 are used as PREAMBLES.

When set to 0, the PREAMBLE_0 and PREAMBLE_1 ports are used.

PREAMBLE_ATTR_0

Std_logic_vector

(31 downto 0)

The PREAMBLE_ATTR_0 and PREAMBLE_ATTR_1 are used when EN_PREAMBLE_ATTR is set to 1.
PREAMBLE_ATTR_1

Std_logic_vector

(31 downto 0)

The PREAMBLE_ATTR_0 and PREAMBLE_ATTR_1 are used when EN_PREAMBLE_ATTR is set to 1.
EN_CF_ADD Std_logic RESERVED. Set to 0.
SAM_VALIDS

Std_logic_vector

(4 downto 0)

Average number of valid bits per clock cycle. The setting 0 is valid for all cases. Setting this number according to use case allows saving resources.
MASK_CG

Std_logic_vector

(15 downto 0)

RESERVED. Leave at default.
MASK_PD

Std_logic_vector

(15 downto 0)

RESERVED. Leave at default.
MASK_VCO

Std_logic_vector

(36 downto 0)

RESERVED. Leave at default.

The following table describes the BCDR core ports.

Table 2. BCDR Core Ports
Port Name Direction and Type Description Comment
Data Flow Ports
CLK In std_logic Clock Core REFCLK, typically from the SerDes
RST In std_logic Reset Active-High
EN In std_logic Enable pin Connected to all internal processes of the BCDR. Set to 1.
DIN In std_logic_vector ((DT_IN_WIDTH -1) downto 0) Input data MSB is conventionally the latest bit coming in. The same convention used in the UltraScale SerDes series.
DV_OUT Out std_logic Output data valid When High, DT_OUT is valid
DT_OUT Out std_logic_vector

(31 downto 0)

Output data MSB is conventionally the latest bit coming in. Data is grouped in 32 or 8 bits.
Configuration Ports
BDW In std_logic_vector

(4 downto 0)

BCDR bandwidth This is the bandwidth of the BCDR in tracking mode. Reducing it by 1 doubles the BCDR bandwidth.
CENTER_F In std_logic_vector (36 downto 0) Center frequency Used to set the fractional ratio between oversampling data rate and incoming data rate
PREAMBLE_0 In std_logic_vector

(31 downto 0)

First preamble pattern First pattern used by the BCDR to estimate the incoming phase of the packet
PREAMBLE_1 In std_logic_vector

(31 downto 0)

Second preamble pattern Second pattern used by the BCDR to estimate the incoming phase of the packet
PAT_MSK In std_logic_vector

(5 downto 0)

Preamble mask A bit in the preamble pattern is used to match when the corresponding bit in the PAT_MSK is set to 1.
AVE_SEL In std_logic_vector

(1 downto 0)

  Depending on this value, a different number of burst bits are used to calculate the burst phase:

00: 1 CLK cycle

01: 2 CLK cycles

10: 4 CLK cycles

11: 8 CLK cycles

Debug Signals
PL_IN In std_logic Inject estimated phase When set to 1 by the user, the LB is steered with the latest estimated phase.
SH_UB_PH In std_logic_vector

(7 downto 0)

UB phase Debug port. Leave at default.
SH_LB_PH In std_logic_vector

(7 downto 0)

LB phase Debug port. Leave at default.
PL_O Out std_logic Burst detected Indicates a preamble has been detected.
BURST_EN In std_logic Burst enable When set to 1, a preamble detection is followed by a phase injection.
DOUT_BST_EN Std_logic Enable on burst data out Debug signal
DOUT_BST Out std_logic_vector

(31 downto 0)

Burst data out Debug signal
PHE_BST_DRU Out std_logic_vector

(15 downto 0)

  Debug signal
PHE_BST_BURST Out std_logic_vector

(15 downto 0)

  Debug signal. Phase profile of incoming packets, as seen by the BCDR
PHE_BST_BURST_AVE Out std_logic_vector

(15 downto 0)

  Debug signal. Average phase profile of incoming packets as seen by the BCDR.
PHASE_OUT Out std_logic_vector

(20 downto 0)

Output VCO phase Debug signal. At each clock cycle, the current NCO phase can be read. The phase is over the 16 least significant bits in signed format.
LTR In std_logic Lock to reference mode Debug signal. When set to 1, the BCDR tracking is disabled.
VCOCTRL Out std_logic_vector

(31 downto 0)

NCO control Debug signal. The control signal of the NCO.
CF_ADD In std_logic Center frequency adder Reserved. Connect to 0.
RECCLK Out std_logic_vector

(79 downto 0)

Recovered clock Debug signal. Can be serialized by a 12.44 Gb/s SerDes to synthesize the bursty recovered clock.
VER Out std_logic_vector

(7 downto 0)

Version This is expected to be 2.
SUB_VER Out std_logic_vector

(7 downto 0)

Sub Version This is expected to be 5.

Additional insights on the BCDR ports and their usage follow. The oversampled and deserialized data enters from DIN and exits from DT_OUT. The output DT_OUT is valid only when DV_OUT is 1.

PL_O is a debug signal that the BCDR pulses to 1 each time it detects a preamble. If a preamble is detected, the NCO is steered to the estimated phase only if BURST_EN is set to 1, which is the default condition.

BDW or BDW_ATTR control the bandwidth of the BCDR during tracking—higher values correspond to lower bandwidth.