BCDR and PHY Configuration - XAPP1277

Burst Clock Data Recovery for 1.25G/2.5G PON Applications in UltraScale Devices (XAPP1277)
Document ID
XAPP1277
Release Date
2024-01-05
Revision
1.2 English

The BCDR circuit described in this section is designed and tested to work in one of the five different cases specified in Table 1. Preset the BCDR to operate in the desired case by setting attributes and input ports of the BCDR as described in Table 1 and Table 2.

Table 1. Five Possible Operating Conditions and Their Attribute Settings
Attribute Name Case 1 Case 2 Case 3 Case 4 Case 5
DT_IN_WIDTH 80 80 80 32 32
DT_OUT_WIDTH 32 32 32 8 8
ENABLE_CENTER_F_ATTR 1 1 1 1 1
CENTER_F_ATTR H800000000 H1000000000 H55555555 H555555555 H666666666
EN_PAT_MSK_ATTR 1
PAT_MSK_ATTR 100000
EN_AVE_SEL_ATTR 1
AVE_SEL_ATTR 01
EN_BDW_ATTR 1
BDW_ATTR 01010
ENABLE_EN 0
ENABLE_LTR_PORT 0
ENABLE_DBG 1
REDUCE_PD 1 0 0 0 0
USE_RED_BRICK 1 0 0 0 0
EN_PREAMBLE_ATTR 1
PREAMBLE_ATTR_0 HAAAAAAAA
PREAMBLE_ATTR_1 HAAAAAAAA
EN_CF_ADD 0
SAM_VALIDS 00000
MASK_CG HFFF0
MASK_PD HFFF0
MASK_VCO H1FFFFFFFF0
Table 2. Port Settings for All Possible Cases
Input Port Name Setting for All Cases
BURST_EN 1
PL_IN 0
SH_UB_PH 00000000
SH_LB_PH 00000000
LTR 0

The BCDR processes oversampled data from a PHY, which is a SerDes. This has to be configured in lock to reference mode, and its auto-adapting equalizer should be disabled. To do that, set the following ports as listed:

  • RXCDRHOLD = 1
  • RXLPMHFOVRDEN =1
  • RXLPMLFKLOVRDEN=1
  • RXOSOVRDEN=1

All these ports are available in the above-mentioned test bench, through virtual input/output (VIO), to properly set the receive CDR and equalizer.

The following section guides you in configuring the GTH SerDes using the UltraScale FPGA Transceiver Wizard in the IP catalog.

Important: Download the most up-to-date IP update before using the wizard. Details on how to use this wizard can be found in UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182).

The Basic tab should be configured as shown in the following figure.

Figure 1. Configuration of the Basic Tab

In the preceding figure, the RX line rate should be set according to the use case as specified in the following table.

Table 3. SerDes Settings for Each Use Case
Case Datapath Line Rate (Gb/s) Oversampling Rate SerDes RX Rate (Gb/s) SerDes REFCLK
1 80 1.244 10 12.4416 155.52 MHz
2 80 2.488 5 12.4416
3 80 2.488 6 14.92992
4 32 1.244 6 7.46496
5 32 1.244 5 6.2208
6 80 1.244 5 6.2208

In the Structural Options tab, ports highlighted in the following figures should be checked so that they are exposed in the generated wrapper.

Figure 2. Ports to be Exposed in the Structural Options Tab
Figure 3. Additional Ports to be Exposed in the Structural Options Tab