Hardware Board Requirements - Hardware Board Requirements - XAPP1267

Using Encryption and Authentication to Secure an UltraScale/UltraScale+ FPGA Bitstream (XAPP1267)
Document ID
XAPP1267
Release Date
2025-05-22
Revision
1.8 English

There are a few basic hardware requirements for implementing an encrypted design flow:

  • For programming ability and debugging capability: A JTAG connection to the FPGA.

  • For BBRAM key storage: Battery to VBATT (see the respective data sheet for battery voltage

    requirements).

  • For eFUSE key storage: VBATT or VCCAUX is recommended to enable the ability to test with

    BBRAM flow prior to burning the one-time programmable (OTP) eFUSEs.