Vivado Project Creation

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

Document ID
XAPP1256
Release Date
2023-12-21
Revision
1.3 English

The Vivado tool works with any standard RTL source files. The regular guidelines are followed to generate a new project and import the RTL source files into the Vivado tool to create a floorplan for the design.

  1. Set up a new Vivado project: From the Quick Start menu, click Create New Project, and wait for the New Project - Create a New Vivado Project window to pop up (see the following figure). Select Next.
    Figure 1. Vivado New Project > Project Name Window
  2. In the New Project - Project Name window enter:
    Project name
    For this lab, the idfLab project name is used.
    Project location
    C:/xilinx_design.
    Note: The Vivado tool automatically changes the Windows directory path separator from \ (back slash) to / (forward slash).
    • Select Create project sub-directory.
  3. Click Next.
  4. Select RTL Project and check the Do not specify sources at this time box (see the following figure).
    Figure 2. Vivado New Project - Project Type Window
    Note: RTL sources are added later.
  5. Click Next.
  6. In the Default Part window, select the appropriate product filters for this lab as listed here and shown in the following table.
    Table 1. Product Filters
    Product category General Purpose
    Family Zynq 7000
    Sub-Family Zynq 7000
    Package clg484
    Speed grade -1
    Temp grade C
    Si Revision All Remaining
  7. Select the xc7z020clg484-1 device.
  8. Click Next and Finish.
    Figure 3. Vivado New Project – Default Part Window
  9. The Vivado project now is created. The following figure shows the Project Manager window for the idfLab project.
    Figure 4. Plan Ahead Project Manager View