Verifying the Routed Design with VIV

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

Document ID
XAPP1256
Release Date
2023-12-21
Revision
1.3 English
Figure 1. Lab Flow Progression - VIV on Final Design

VIV is run on the implemented design to catch isolation faults between isolated regions, as well as package pin and I/O bank violations (as when VIV was run on the floorplanned design). The steps in this section guide you through the process.