Synthesis Process

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

Document ID
XAPP1256
Release Date
2023-12-21
Revision
1.3 English

This section describes the synthesis process. In this lab, though time consuming, synthesis is not a significant part of the process. This is because all the IP was created earlier and you are only assembling the blocks. If done correctly, the synthesis schematic should look the same as the RTL schematic.