Summary

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

Document ID
XAPP1256
Release Date
2023-12-21
Revision
1.3 English

This lab application note describes the creation and implementation of a single chip cryptography (SCC) system using redundant Keccak hash modules with compare logic. Complete step-by-step instructions are given for the entire process, explaining the use of the Isolation Design Flow (IDF). This document explains how to implement isolated functions in a single AMD Zynq™ 7000 SoC device for the example SCC solution. Even though this application note explains how to implement a design using the IDF for a Zynq 7000 device, the same process can be used to implement an IDF design using any 7 series FPGA device.

With this application note, designers can develop a fail-safe single chip solution using the IDF that meets fail-safe and physical security requirements for an example high-assurance application. This application note is similar to the application note 7 series Isolation Design Flow Lab Using ISE Design Suite 14.4 (XAPP1085) with the primary difference being this document is specific to using the AMD Vivado™ Design Suite for Zynq 7000 SoC devices, whereas 7 Series Isolation Design Flow Lab Using ISE Design Suite 14.4 (XAPP1085) is specific to using the AMD ISE® Design Suite for developing IDF designs for 7 series FPGA devices. The rules for IDF defined in this application note do not differ from those defined in XAPP1085, but the methodology for implementation using Vivado tools does.

This application note is accessible from the Isolation Design Flow website. Download the Reference Design Files for this application note from the AMD website. For additional information about the design files, see Reference Design Files.