Running VIV Against the Floorplan

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

Document ID
XAPP1256
Release Date
2023-12-21
Revision
1.3 English
Figure 1. Lab Flow Progression: VIV on Floorplan

The AMD Vivado Isolation Verifier (VIV) software verifies that FPGA or SoC designs that have been partitioned into isolated modules meet the stringent standards for a fail-safe design. VIV is a Tcl script that runs in the Vivado tool framework in the form of DRCs. This allows for a strong GUI interface to the tool that was not available in the older ISE tools for IVT.

VIV is run on the floorplan to catch pin, I/O bank, and area group isolation faults early in the design, when changes are more easily integrated. The steps in this section guide you through the process. After implementation, the VIV is run against the routed design.