Routing Resources View (Comments on the Mode)

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

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1.3 English
These steps describe how to generate and run a design implementation.
Figure 1. Enabling/Disabling Routing Resources Mode – Device View

Gaps in the floorplan appear in this view because the tools do not consider the interconnect tiles associated with all user tiles as part of the pblock. This is visual only; the gaps do not exist.

In this view, you can track a schematic net to the routed net. This is a very powerful view when tracing timing issues.

Also, from this view you can manually route any component or net as you wish. This mode is the Vivado replacement to the ISE FPGA Editor. The replacement is significantly more user friendly.

It is possible for routes, not touchdowns, from one isolated region to cross over into another isolated region if the region in question does not have any routing in that area. This allows for maximum flexibility to the router while still obeying IDF rules for isolation. This only happens in designs where sparsely populated isolated regions are adjacent to regions that are densely populated. No placement or touchdowns are ever allowed outside the intended isolated region.