The following table shows the revision history for this document.
Section | Revision Summary |
---|---|
12/21/2023 Version 1.3 | |
Install Reference Design Files into Target Directories | Provided complete directory path in Step 1. |
Creating a Vivado IP Integrator Project | Removed outdated information in Step 2. |
Floorplanning the System | Removed unnecessary spaces throughout codes in Step 4 and Step 5. |
10/20/2023 Version 1.2 | |
Creating an IP Integrator Block Design | Updated Step 8.c. connection from data0_valid to data1_valid. |
Verifying the Floorplan with VIV | Removed Step 1. |
Implementing the Design | Updated Vivado Implementation to 2023. |
Verifying the Routed Design with VIV | Removed Step 1. |
03/21/2016 Version 1.1.1 | |
Throughout Document | Updated the title to clarify support for 7 series FPGAs. |
02/24/2016 Version 1.1 | |
Verifying the Floorplan with VIV | Updated the title, Figure 28, and Figure 38. |
03/21/2016 Version 1.0 | |
Initial Xilinx release. | N/A |