Download the Reference Design Files for this application note from the Xilinx website.
The reference design matrix in the following table indicates the tool flow and verification procedures used for the provided reference design.
Parameter | Description |
---|---|
General | |
Developer name | AMD |
Target device | Zynq 7000 XC7Z020 SoC |
Source code provided | Yes |
Source code format | VHDL |
Design uses code or IP from existing reference design, application note, third party, or Vivado software? If yes, list. | No |
Simulation | |
Functional simulation performed? | Yes |
Timing simulation performed? | Yes |
Test bench used for functional and timing simulations? | Yes |
Test bench format | VHDL |
Simulator software and version used | Vivado Design Suite 2023.1 |
SPICE/IBIS simulations? | No |
Implementation | |
Implementation software tools and versions used | Vivado Design Suite 2023.1 |
Static timing analysis performed? | Yes |
Hardware Verification | |
Hardware verified? | No |
Hardware platform used for verification | N/A |