Open the Elaborated Design

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

Document ID
XAPP1256
Release Date
2023-12-21
Revision
1.3 English

Just under the IP Integrator section is the Simulation section and then the RTL Analysis section.

  1. Click the Open Elaborated Design menu item. This launches the process. When complete, a large block diagram labeled design_1_i will appear. This is the default name generated by IP integrator when the HDL wrapper was added.
  2. Navigate to your design by clicking + at the top left of any block to open hierarchies. The following figure shows an example of one hierarchy opened.
    Figure 1. RTL Schematic (expanded)
  3. Add some attributes to tell the tools which modules are going to be isolated using IDF. This is done with the HD.ISOLATED attribute. This attribute not only evokes the IDF routing rules, but also protects redundant modules from undesired optimization. Synthesis optimization cannot happen across an HD.ISOLATED boundary. It can happen within one, but that is typically desired.
  4. Expand the design_1_i instance in the Netlist tab so each of the modules created in IP integrator are visible as shown in the following figure.
  5. Select keccak_0_ISO_Wrapper.
    1. Right-click and select Cell Properties (if this window is not already visible).
    2. Select the Properties tab in the Cell Properties window.
    3. Click the green + and add the attribute HD.ISOLATED from the Add Properties pop-up window.
    4. Expand the newly added attribute and check the unchecked check box as shown in the following figure.
    Figure 2. Setting HD.ISOLATED Attribute
  6. Repeat Step 5 for keccak_1_ISO_Wrapper.
  7. Repeat Step 5 for keccakCompare_0_ISO_Wrapper.
  8. Repeat Step 5 for ps7_ISO_Wrapper.
  9. Save the design and enter Top when requested, to enter the file name of the Xilinx design constraints (XDC) file
  10. Select OK.