Lab Design Overview

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

Document ID
XAPP1256
Release Date
2023-12-21
Revision
1.3 English

The 7 series and Zynq 7000 IDF rules are outlined in Isolation Design Flow for 7 series FPGAs or Zynq 7000 SoCs (Vivado Tools) (XAPP1222). Though the rules for IDF do not differ between ISE and Vivado, the methodology for implementation using Vivado tools does differ.

This lab gives details on how functions are to be isolated, specific differences between a normal partition flow and an IDF partition flow, information on IDF-specific hardware description language (HDL) code mnemonics, and trusted routing rules.

To illustrate the IDF and its capabilities, this design implements isolated, redundant Keccak hash modules with a compare block. The following figure is a hierarchical diagram of the various VHDL sub-blocks used in the implementation of this design.

Important: Use Vivado Integrated Design Environment (IDE) 2018.3 or later for this lab.
Figure 1. Design Hierarchy Block Diagram

The following figure shows the flow used during the course of this lab. The fundamental goal is to give you an idea of what the methodology looks like in Vivado tools and how tools such as Vivado IP integrator can be of significant help (see Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994).

Figure 2. Vivado IDF Lab Flow Using IP Integrator as the Primary Source Generator

The following figure shows the floorplan for the lab design as implemented in an xc7z020clg484-1 device. It consists of four area groups. The first is an area group that contains the PS7 site ( ArmĀ® Dual Core A9 Processing System) and some additional space to route as needed, such as Advanced eXtensible Interface (AXI) signals. The other three represent a typical redundant system with compare module whose clocks and resets come from the processor.

Important: When putting the PS7 in an area group, at the very minimum, create a fence on the full right side of the PS7 block and include the first CLB tile on the lower right corner under the PS7 block. See Isolation Design Flow for Xilinx 7 Series FPGAs or Zynq 7000 SoCs (Vivado Tools) (XAPP1222), PS Fence Tile section, for more details.

Signals from the PS7 can only get to the FPGA fabric on the right side of the PS7 site. If you need to communicate to an area group below the PS7, you need to have added some of the fabric on the right and bottom to allow communication to and from the PS7.

Figure 3. Die View: IDF Lab Floorplan in an xc7z020clg484-1 Device