Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

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1.3 English

The Isolation Design Flow is the software methodology that allows for SCC implementations or any other application requiring the module have both physical and logical isolation. This methodology is backed by significant schematic analysis and software verification—Vivado Isolation Verifier (VIV)—to ensure elimination of single points of failure. SCC is one specific application of IDF allowing the implementation of a multichip cryptography system in a single FPGA or SoC.

Note: Procedure works with Vivado versions 2018.3 and later.