Floorplan Process

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

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1.3 English

The floorplan of the reference design is shown in the following figure. Where inter-module communication (via Trusted Routing) is necessary, regions must be coincident with each other with a fence tile between the two intended regions.

Figure 1. Floorplan of the Reference Design Highlighting the Trusted Routing Channels

Floorplanning a design is the most time consuming part of the Isolation Design Flow. The purpose of this lab is not to test your skills in creating pblocks and placing pins, but to allow you to become familiar with the flow itself and how it integrates well in into IP integrator.

Scripts are provided that allow you to generate the floorplan in a few minutes rather than a few hours. Still, it is very important to understand the floorplanning rules and complexities that are associated with floorplanning any design ( Vivado Design Suite User Guide: Dynamic Function eXchange (UG909) and Vivado Design Suite User Guide: Hierarchical Design (UG905). More details on the IDF rules are in Isolation Design Flow for Xilinx 7 Series FPGAs or Zynq 7000 SoCs (Vivado Tools) (XAPP1222).

  1. Select the Tcl Console tab at the bottom of the Vivado GUI.
  2. Enter the following commands:
    1. cd c:/xilinx_design (if not already in this directory)
      Note: This assumes you extracted the lab design into c:/xilinx_design.
      Note: Make sure to use the Linux "/" instead of the Windows "\" when using the Vivado tool command language (Tcl) (see Vivado Design Suite Tcl Command Reference Guide (UG835) for more information).
    2. source ./sources/xdc/pins.xdc
    3. source ./sources/xdc/k0.xdc
    4. source ./sources/xdc/k1.xdc
    5. source ./sources/xdc/compare.xdc
    6. source ./sources/xdc/controller.xdc
    Note: There might be a warning for No Pblocks matched, which is due to the first XDC command in the file querying if the Pblock already exists. If so, delete it before creating a new Pblock.
  3. Save the design, selecting OK and YES. When complete, your floorplan looks like the following figure.
    Figure 2. Completed Lab Design Floorplan
  4. Save the design.

    An enhancement to IDF in Vivado is designed to allow global clocking components inside isolated modules. Global components cannot actually be isolated due to their global scope. Before IDF in Vivado, you had to modify their design and ensure such components were at the top level of their design. IDF in Vivado allows for attributes to be set to turn off isolation on them, allowing them to be nested but not isolated. This is particularly useful for clocks coming from the Zynq 7000 processing system (PS) region because they cannot be moved. In this design, all clocks and resets are generated by the PS region. To turn off isolation of the clocks, use the following command:

    set_property HD.ISOLATED_EXEMPT true [get_cells –hierarchical –filter {PRIMITIVE_TYPE =~ CLK.gclk.*}]

    In this example the HD.ISOLATED_EXEMPT property is applied globally to any and all clock components in your design. If your design has some clock components that you desire to be isolated, the safer method is to exempt only the ones in the processor block. This is accomplished by adding an additional item to the -filter option. The more restrictive filter option now looks as follows:

    -filter {NAME =~ *ps7* && PRIMITIVE_TYPE =~ CLK.gclk.*}

  5. The new Tcl command is shown below. Enter the following statement in the Tcl Console window:
    set_property HD.ISOLATED_EXEMPT true [get_cells
    –hierarchical –filter {NAME =~ *ps7* && PRIMITIVE_TYPE =~ CLK.gclk.*}]
  6. Save the design by selecting OK and YES.
  7. Browse the floorplan around the fences, verifying the fence rules (no less than one user tile).