Final Isolation Verification (VIV - Implementation)

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

Document ID
XAPP1256
Release Date
2023-12-21
Revision
1.3 English

After the design is complete (placed and routed), VIV is used again on the implemented design to validate that the required isolation was built into the design.

At this step, VIV checks the following:

  • VIV analyzes the complete placed and routed design.
  • Tile-based isolation analysis looks for a barrier (fence) between isolated regions.
    • A valid user tile acts as a sufficient isolation barrier if:
      • It does not contain any isolated signals (from any isolated region).
      • It is configured in the default (unused) state.
  • VIV does the same pin and I/O checking as in Floorplan mode.